1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device consisting of twin memory cells, each including one word gate and two non-volatile memory elements controlled by two control gates, as well as to a method of actuating such a non-volatile semiconductor memory device.
2. Description of the Related Art
A known non-volatile semiconductor memory device that is capable of electric writing (programming) and erasing is MONOS (metal-oxide-nitride-oxide-semiconductor or -substrate) type, where a gate insulating layer between a channel and a gate is a laminate of a silicon oxide film, a silicon nitride film, and a silicon oxide film and the silicon nitride film traps electric charges.
The MONOS-type non-volatile semiconductor memory device is disclosed in a reference Y. Hayashi et al, 2000 Symposium on VLSI Technology Digest of Technical Papers p.122-123). This cited reference describes a twin MONOS flash memory cell having one word gate and two non-volatile memory elements (also be referred to as MONOS memory elements or cells) controlled by two control gates. Namely one flash memory cell has two trap sites of electric charges.
The MONOS-type non-volatile semiconductor memory device includes multiple twin MONOS flash memory cells of such structure, which are arrayed in rows and columns.
This non-volatile semiconductor memory device (flash memory) carries out data reading, writing (programming), and erasing operations. The data programming operation and the data reading operation are typically performed by the unit of 1 byte (8 bits) or by the unit of 1 word (16 bits). The procedure of the data programming operation or the data reading operation simultaneously selects 1 byte of or 1 word of non-volatile memory elements and simultaneously writes or reads data into or from these selected non-volatile memory elements (selected cells). The respective bit signals corresponding to these selected cells are input and output via I/O lines.
The semiconductor memory device has a data read access function called xe2x80x98burst modexe2x80x99. The procedure of reading data from the semiconductor memory device in the burst mode specifies one address of the semiconductor memory device and generates multiple address signals sequentially varying from the specified address as the reference. The procedure then successively reads the contents of the memory elements (memory cells) corresponding to the sequentially varying addresses.
The prior art twin MONOS-type non-volatile semiconductor memory device, however, does not have the function of reading data in the burst mode. There is accordingly a demand of developing such a twin MONOS-type non-volatile semiconductor memory device having the function of reading data in the burst mode.
In order to solve the drawbacks of the prior art discussed above, the object of the present invention is to provide a non-volatile semiconductor memory device of twin memory cells having the function of reading data in a burst mode.
In order to attain at least part of the above and the other related objects, a first application of the present invention is directed to a non-volatile semiconductor memory device, which includes: a memory cell array having multiple twin memory cells arrayed both in a row direction and in a column direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; multiple word lines, each of which is provided for each row of the memory cell array and is shared by the word gates of plural twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in the column direction; an address generation circuit that generates multiple addresses varying sequentially from a specified address; an access control circuit that regulates operations of at least the multiple word lines and the multiple bit lines according to the multiple addresses generated by the address generation circuit, so as to control a reading operation of information; and a detection circuit that detects information read via the multiple bit lines.
In the process of selecting the sequentially varying multiple addresses to read information from non-volatile memory elements corresponding to the multiple addresses, the access control circuit causes plural non-volatile memory elements arrayed in the column direction on a preset column to be selected sequentially according to the varying multiple addresses, among the multiple non-volatile memory elements arrayed in the row direction and in the column direction.
The non-volatile semiconductor memory device of the first application generates multiple addresses sequentially varying from a specified address and successively reads information from non-volatile memory elements corresponding to the generated multiple addresses. This arrangement actualizes the non-volatile semiconductor memory device of twin memory cells having the functions of reading data in a burst mode.
In the non-volatile semiconductor memory device of the first application, non-volatile memory elements of different rows connecting with an identical bit line are successively selected according to the sequentially varying addresses. Compared with an arrangement of successively selecting non-volatile memory elements connecting with multiple different bit lines, the arrangement of successively selecting the non-volatile memory elements of different rows connecting with an identical bit line effectively reduces the total power consumption of the non-volatile semiconductor memory device.
A second application of the present invention is directed to a method of actuating a non-volatile semiconductor memory device. Here the non-volatile semiconductor memory device includes: a memory cell array having multiple twin memory cells arrayed both in a row direction and in a column direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; multiple word lines, each of which is provided for each row of the memory cell array and is shared by the word gates of plural twin memory cells arrayed in the row direction; and multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in the column direction.
In the process of selecting the sequentially varying multiple addresses to read information from non-volatile memory elements corresponding to the multiple addresses, the method includes the step of: causing plural non-volatile memory elements arrayed in the column direction on a preset column to be selected sequentially according to the varying multiple addresses, among the multiple non-volatile memory elements arrayed in the row direction and in the column direction.
Like the non-volatile semiconductor memory device in the first application, the method of actuating the non-volatile semiconductor memory device in the second application enables information of non-volatile memory elements to be successively read according to the multiple addresses sequentially varying from the specified address. This arrangement actualizes the non-volatile semiconductor memory device of twin memory cells having the functions of reading data in a burst mode. The method of the second application causes non-volatile memory elements of different rows connecting with an identical bit line to be successively selected according to the sequentially varying addresses. Compared with an arrangement of successively selecting non-volatile memory elements connecting with multiple different bit lines, the arrangement of successively selecting the non-volatile memory elements of different rows connecting with an identical bit line effectively reduces the total power consumption of the non-volatile semiconductor memory device.
The above and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiment with the accompanying drawings.